ARM (Advanced RISC Machines) Processors

History
ARM machines have a history of living up to the expectations of their developers, right from the very first ARM machine ever developed. It all began in the 1980s when Acorn Computers Ltd., spurred by the success of their platform BBC Micro wished to move on from simple CMOS processors to something more powerful, something that could stand strong against the IBM machines launched in 1981. The solutions available in the market like the Motorola 68000 were not powerful enough to handle graphics and GUIs leaving only one option with the company, make their own processor.

Inspired by the making of 32 bit processors by some undergraduates at Berkeley and a one man design center Western Design Center, Phoenix, Steve Furber and Sophie Wilson of Acorn Ltd. set out to make their own processors. Sophie developed the instruction set and simulated it on the BBC Basic which convinced many in the company that it was not just anything half hearted shot aimed in darkness. With the support and permission of the then CEO Hermann Hauser, the ARM project formally took off in 1983 with VLSI Technology as their silicon partner, to produce an ARM processor with latencies as low as that of the 6502. The first ARM core dubbed as ARM1 was delivered by VLSI Technology in 1985. This processor used in conjunction with the BBC Micro helped in the development of the next generation called ARM2. 1987 saw the release of ARM Archimedes.

Acorn floated a new company Advanced RISC Machines Ltd. solely dedicated for ARM core development. In 1992, Acorn won the Queen’s Award for Technology for the ARM. Apple and ARM collaborated to develop the ARM6 cores on which the Apple Newton PDAs were based. Later, the technology was also transferred to Intel over a settlement of lawsuit. Intel further modified it and developed its own high performance line XScale, now sold to Marvell. ARM Inc. is involved with developing cores primarily while its licensees make microcontroller and processors, the most popular being the ARM7TDMI machines. Some prominent licensees of ARM machines are Alcatel Lucent, Apple, Atmel, Cirrus Logic, Freescale, DEC, Intel, LG, Marvell, Microsoft, Nvidia, Qualcomm, Samsung, Sharp, ST microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha, Zilabs etc.


ARM machines have a 32 bit Reduced Instruction Set Computer (RISC) Load Store Architecture. The relative simplicity of ARM machines for low power applications like mobile, embedded and microcontroller applications and small microprocessors make them a lucrative choice for the manufacturers to bank on. The direct manipulation of memory isn’t possible in this architecture and is done through the use of registers. The instruction set offers many conditional and other varieties of operations with the primary focus being on reducing the number of cycles per instruction featuring mostly single cycle operations.

All instructions in the ARM ISA are conditional with the normal execution instructions also being accompanied by condition AL. There are 14 conditions available excluding AL. The instruction set added many feathers to its cap as and when the generations grew. The transistor count has also increased substantially from 30000 in ARM2 to about 26 million in Cortex-A9 ARM. An additional Thumb architecture was developed to support 16-bit instruction models on the otherwise 32 bit ARM machines. No matter the added advantage of increased code density which was about 65% of the original ARM code, this resulted in a little performance drop in the ARM machines. This drop was somewhat balanced with Thumb 2 which was a major extension over the Thumb ISA.

In Thumb 2, the compiler automatically selects a mixture of 16 bit and 32 bit instructions. It is to be noted that only the instruction set changes from 32 bit to 16 bit, the core continues to operate at 32 bit. The evolution of ARM v7 cores saw the development of Thumb Execution Environment (Thumb-EE) which offered dynamic coding by compiling the code moments before or during execution itself. Thumb feature is basically another Instruction Set running on the same platform. Another Instruction set, to execute Java codes on ARMs was developed soon and was named Jazelle. These three Instruction sets are now the three states on an ARM core and to shift from one state to another, directives like ARM, THUMBX and THUMB are given to the assembler.

ARM Architecture
ARM machines have a 32 bit Reduced Instruction Set Computer (RISC) Load Store Architecture. The relative simplicity of ARM machines for low power applications like mobile, embedded and microcontroller applications and small microprocessors make them a lucrative choice for the manufacturers to bank on. The direct manipulation of memory isn’t possible in this architecture and is done through the use of registers. The instruction set offers many conditional and other varieties of operations with the primary focus being on reducing the number of cycles per instruction featuring mostly single cycle operations.

All instructions in the ARM ISA are conditional with the normal execution instructions also being accompanied by condition AL. There are 14 conditions available excluding AL. The instruction set added many feathers to its cap as and when the generations grew. The transistor count has also increased substantially from 30000 in ARM2 to about 26 million in Cortex-A9 ARM. An additional Thumb architecture was developed to support 16-bit instruction models on the otherwise 32 bit ARM machines. No matter the added advantage of increased code density which was about 65% of the original ARM code, this resulted in a little performance drop in the ARM machines. This drop was somewhat balanced with Thumb 2 which was a major extension over the Thumb ISA.

In Thumb 2, the compiler automatically selects a mixture of 16 bit and 32 bit instructions. It is to be noted that only the instruction set changes from 32 bit to 16 bit, the core continues to operate at 32 bit. The evolution of ARM v7 cores saw the development of Thumb Execution Environment (Thumb-EE) which offered dynamic coding by compiling the code moments before or during execution itself. Thumb feature is basically another Instruction Set running on the same platform. Another Instruction set, to execute Java codes on ARMs was developed soon and was named Jazelle. These three Instruction sets are now the three states on an ARM core and to shift from one state to another, directives like ARM, THUMBX and THUMB are given to the assembler.